Yuri Panchul (panchul) wrote,
Yuri Panchul
panchul

Я тоже иногда ностальгирую. Но не по СССР.

Yuri Panchul 1998Тут в ЖЖ толпы каких-то людей ностальгируют по СССР, при котором они ели колбасу по 2.20 и их девушки любили. С моей точки зрения до-горбачевский СССР был довольно унылым местом, хотя и с вкраплениями определенных интересных людей и явлений (другим таким местом наверное является Северная Корея). По СССР я не ностальгирую, но объект ностальгии у меня есть. Это время 1997-1998 годов, когда я начинал свою компанию. Я ее начал в спальне своей тогдашней маленькой квартиры, инкорпорировал, а после получения инвестмента и наема профессионального CEO я стал CTO. Вспоминаю первых частных инвесторов, первую встречу с венчурными капиталистами, первый офис, первую выставку, первых клиентов (Fujitsu и Hitachi) - все это было свежо и прекрасно. Одновременно я стал сожительствовать с Саякой, потом мы поженились, у нас родился первый ребенок и т.д. Вот вытащил пару статей о том времени и ностальгирую:


Electronic Engineering Times, Jan 26, 1998
Startup offers alternative to behavioral synthesis at DesignCon
By Richard Goering
http://eetimes.com/news/98/991news/startup.html

Electronic News, Feb 22, 1999
C Level Design Bulks Up Management
http://findarticles.com/p/articles/mi_m0EKF/is_2258_45/ai_54068078


Posted: 6:00 p.m. EST, 1/26/98
Startup offers alternative to behavioral synthesis at DesignCon

By Richard Goering

SANTA CLARA, Calif. -- Startup CompiLogic Corp. (San Jose, Calif.) will introduce a product at this week's DesignCon 98 show that could make system-level design a lot easier. The company will unveil a compiler that claims to automatically translate C-language descriptions into synthesizable register -transfer level (RTL) Verilog.

CompiLogic's product, called C2Verilog, addresses a major gap in the design process today--the inability to automatically go from C-language models to HDLs. As such, it provides an alternative to behavioral-synthesis products that take high-level Verilog or VHDL descriptions, suggesting instead that designers go directly from C to RTL code.

In addition to demonstrating its software, CompiLogic is offering a DesignCon 98 technical paper on the new technology. The paper illustrates the use of C2Verilog to translate compression-decompression, prime number and sorting algorithms, using an evaluation board with a Xilinx 4010 device to assess performance and hardware-resource utilization.

Privately funded CompiLogic is headed by Don Soderman, chief executive officer, who has held executive posts at IBM, LSI Logic, Intel and Xilinx; Denis Coleman, chairman of the board, a cofounder of Symantec Corp.; and Yuri Panchul, chief technical officer, a compiler expert who helped d evelop Mentor Graphics' Seamless co-verification environment.

"We have a different approach to developing software than traditional EDA vendors who have focused on HDLs," said Soderman. "We've combined expertise with C compilers with EDA experience."

Labor saver
Soderman noted that C is the most widely used behavioral language, largely because complex systems can be described in a very small amount of code. However, manual translations to VHDL or Verilog are "very laborious," he noted. To address this problem, CompiLogic is selling C2Verilog along with an evaluation board that can contain a Xilinx or Lucent FPGA, along with a demonstration version of Synopsys' FPGA Express synthesizer.

Beyond C2Verilog, which is available for shipment today, the company plans to support VHDL in the future and to offer more debugging capability, Soderman said. The company has been developing its technology since early 1997.

Automatic code generation always involves some sort of tradeoff, and C2Verilog is no exception. "It's not as efficient as if you hand wrote it," said Soderman. "It's like compiling C vs. writing assembly code. But the time savings is significant."

The company doesn't yet have specific metrics on code efficiency vs. time savings. An LZW compression/decompression algorithm described in the DesignCon paper was synthesized into a Xilinx 4013 at 72 percent CLB utilization with a 20-MHz clock, and into an LSI Logic 300K ASIC, where the logic took around 6,500 gates and ran at 80 MHz. The paper quotes a compilation speed over 10,000 gates per minute.

The compiler claims to support the full ANSI C specification, including such C-language constructs as pointers, loops and functions--a breakthrough capability, according to Soderman. It allows concurrency through global analysis and optimization, which can determine how parameters are used and create state machines as needed for sequential blocks.

The best results are achieved if user s follow some C-coding guidelines. For instance, if the designer wants to run two functions in parallel, those C functions cannot write into the same C variable. The product also comes with a graphical user interface, letting users specify such things as bit width and use of signed or unsigned variables.

Verilog state machines
Users can exert fairly tight control over the translation by using single multipliers with multiplexers. The compiler automatically creates multiple Verilog state machines for loops, on-chip register and arithmetic macros, and external memory interfaces. The DesignCon paper describes a two-pass compilation interface with a synthesis tool that allows the insertion of registers and wait states to balance propagation delays for best performance.

Since C2Verilog schedules operations into clock cycles, and allocates resources, it performs many of the functions of behavioral-synthesis products.

One methodology question posed by the translator is where the "golden m odel" resides. If it's the C-language model, then users should not change the generated RTL Verilog code unless they're prepared to update the C model. This updating is not handled automatically. The approach Soderman suggests is to run the C code through the compiler with different options to get the best result, rather than editing the RTL code.

C2Verilog is available on Unix and Windows NT or 95 platforms for $9,500, and has been used by the NASA Jet Propulsion Lab in Pasadena, Calif. CompiLogic has a Web site .





C Level Design Bulks Up Management
Electronic News , Feb 22, 1999
Company names Park, Harding and Baynes to senior management team.

C Level Design, Inc. recently announced three executive hirings, bolstering the company's senior management team. The company has appointed electronics and electronic design automation (EDA) industry veterans David Park, Martin Harding, and Martin Baynes to the positions of vice president of worldwide marketing, vice president of worldwide sales, and vice president of worldwide engineering, respectively. Together with C Level Design's president and chief executive officer, Daniel Skilken, and its chief technology officer, Yuri Panchul, the company's executive management team boasts more than 94 years of combined industry experience including senior management posts at Synopsys, Mentor Graphics, Cadence, and Summit Design.

"We've put together a world-class executive management team to drive our organization into the next millennium," Skilken said. "Beyond their strong backgrounds and outstanding individual talents, the new members of our management team bring a tremendous track record of technical and business success to C Level Design."

Park has more than 13 years of development and marketing experience in the electronics and EDA industries. Prior to joining C Level Design, Park was group marketing manager of Synopsys' High Level Verification Group, responsible for Synopsys' hardware/software co- verification products. In his two years at Synopsys, Park moved the co-verification business from a distant second place in the market to number one in product sales. Prior to Synopsys, Park was the director of technical marketing for Summit Design.

Before joining Summit, Park was an applications engineering consultant in the sales organization of Mentor Graphics, and a member of the technical staff at the Autonetics Marine Systems Division of Rockwell International.

Harding has over 28 years of experience in sales and marketing in the EDA and semiconductor industries. Before joining C Level Design, Harding was the vice president of worldwide sales for Ambit Design Systems, which was acquired by Cadence Design Systems. At Ambit, he built a distribution channel of 36 direct sales people and six international distributors. Harding drove Ambit's sales to $12 million in the first year in head-to-head competition with Synopsys, making Ambit the fastest growing company in EDA history. Prior to Ambit, Harding was the vice president of sales and marketing for VirtualChips, a provider of synthesizable cores and semiconductor intellectual property (IP).

Before joining Virtual Chips, Harding was the vice president of sales for Chronologic Simulation (acquired by Viewlogic Systems). He drove Chronologic's sales from $4.9 million to $18 million in one year in direct competition with Cadence. Prior to Chronologic, he was director of the ASIC Business Group for Cadence and Gateway Design, and established Verilog as the de facto simulation standard for ASIC and system development.

Baynes has over 25 years of experience in engineering management in both EDA and electronic design. Before joining C Level Design, Baynes was the vice president of engineering operations for Aspec Technology, a library IP provider to semiconductor companies. Prior to Aspec, Baynes was the vice president of engineering for Zycad where he managed all simulation acceleration product development and support. At Zycad, he managed the development of over 22 major software and hardware releases for 12 products, including a super- scalar simulation accelerator.

Before joining Zycad, Baynes was director of engineering for simulation and synthesis products at GenRad Design Automation, and also was the director of engineering for ASIC development for National Semiconductor in Europe.

C Level Design, Inc. is a privately held company founded in 1997 to develop and market system-level design automation software products for electrical engineers. The company's products enable engineers to design and verify systems at the C level and then automatically compile their designs to HDL code that is compatible with industry standard synthesis tools from Synopsys, Cadence, and Mentor Graphics.

COPYRIGHT 1999 Reed Business Information, Inc. (US)
COPYRIGHT 2008 Gale, Cengage Learning



Стартап был куплен во время кризиса после 9/11 большой компанией Synopsys. Второго стартапа в области EDA я делать не буду, так как время для EDA стартапов ушло, да и облом. Нахожу новые развлечения.
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