I was able to comfortably fit MIPSfpga into DE1 using my variation of MIPSfpga Getting Started / Fundamentals package. I can show you how you can reproduce my result and then how you can correct your own port of MIPSfpga Getting Started by borrowing some of the components I have created.
First, here is how to reproduce my result:
- Unzip MIPSfpga Getting Started to C:\MIPSfpga
- Get mipsfpgfa-plus into C:\github\mipsfpga-plus
- cd C:\github\mipsfpga-plus\boards\de1
- Run Altera Quartus II version 13.0 sp1
- Open project C:\github\mipsfpga-plus\boards\de1\proje
- Open Device / Hardware Setup / ByteBlaster / Set file / ouput_files / de1.sof / Start
You should get the following:
Note I do not have a DE1 board with me so I did not test running on the board. However I am confident it will run either immediately or after I adjust my clock divider.
Now how to correct your own port of DE1:
- First, I noticed that you have two versions of mipsfpga_ahb_const.vh with different sizes for ram and reset_ram. This is OK if you have a proper “set_global_assignment -name SEARCH_PATH” line in your .qsf file. Does Quartus pick the correct .vh file?
- I was able to fit the design comfortably by specifying 1KB reset_ram size and 1 KB user ram size. However the boot/reset sequence in the original MIPSfpga Getting Started does not fit into 1 KB because it is linked with crt0 from the standard C library. This crt0 code is totally unnecessary because its function is to setup C runtime in “big” operating systems before calling main() and most of it is not applicable for MIPSfpga. By omitting calling crt0 and setting up a stack pointer inside the boot sequence itself, it is possible to shrink the boot sequence to 1KB. You can get it here – https://github.com/MIPSfpga/mipsfpga-plus/blob/master/programs/00_counter/boot.S
- Now you may say that 1 KB for user ram is too small. Still, it is enough to do many lab exercises, and if you need more, it is possible to write an interface to the 8 MB SDRAM present on the DE1 board.
- Also, if you need more block ram, it is possible to eliminate EJTAG module and load the software program into your synthesized system via UART present in DE1 board.
- Options like “set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON” can bloat the design. If you use it, this would explain why you cannot fit. You can see my constraint file right here - https://github.com/MIPSfpga/mipsfpga-plus/tree/master/boards/de1
- I got Fmax 45.97 MHz on my synthesis so you may need to adjust PLL to divide 50 MHz clock.
- If necessary, I can sit with you over Skype and make sure you fit the MIPSfpga into DE1 and can run it. My Skype is yuri.panchul.
The whole thing is doable we just need to avoid the pitfalls I outlined (bloating options in constraint file, proper sizes for memories, compact bootloader, clock divider).
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