На фотках ниже вы можете увидеть меня у здания МИЭТ-а в Зеленограде и Cadence в Сан-Хосе:
12-ого марта Cadence и МИЭТ в Зеленограде проводят Technology Day с такими темами:
09:00 – 09:15 Registration
09:15 – 09:45 Introduction from Cadence
09:45 – 11:15 Electrically-aware Design: A new methodology for addressing the growing complexity of electrical verification in IC design
The larger challenge for today’s design teams is to improve design productivity
while differentiating their products to take advantage of silicon advances. New analog
mixed-signal design methodologies are needed that can ensure design intent is met and
that the layout is electrically correct by construction. An electrically aware design
methodology will be presented that may reduce design time significantly and allow
designers to take greater advantage of new advances in silicon technology.
11:15 – 11:30 Coffee-Break
11:30 – 12:30 Advances in MMSIM Circuit Simulation Technology
An update will be given about advances in MMSIM Circuit Simulation
Technology, including parallel and fast SPICE simulation technology, advanced
design checks and checking infrastructure, EMIR postlayout simulation and
12:30 – 13:30 Lunch
13:30 – 14:45 Cadence® Tempus™ Timing Signoff
The Tempus Timing Signoff Solution provides full-chip static timing analysis (STA) with gate-level delay calculation, signoff-level timing and signal integrity (SI) analysis, statistical timing and leakage analysis, advanced on-chip variation analysis and the advanced node functionality required for double-patterning and waveform effects. It addresses the timing closure challenges introduced from the increased analysis complexities and capacities and provides up to 10X productivity improvement in design closure. Cadence® Tempus™ Timing Signoff Solution offers massively parallelized timing analysis and physically aware multi-mode, multi-corner optimization for faster design closure and signoff. It is a complete standalone tool that delivers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout. By tightly coupling the design implementation environment with the timing signoff environment, the Tempus solution enhances timing convergence throughout the design flow and greatly reduces the time to design closure. It shrinks timing signoff closure and analysis for faster tapeout while producing designs with less pessimism, area, and power consumption. Tempus enables SoC developers to speed timing closure and move chip designs to fabrication quickly.
14:45 – 15:00 Coffee Break
15:00 –16:15 Encounter Digital Implementation Overview (What’s new)
The Encounter Digital Implementation (EDI) provides an integrated solution for an RTL-to-GDSII design flow. EDI brings performance to new levels. Next-generation technology such as GigaPlace, CCOpt, GigaOpt, TrackOpt, provide better PPA, utilization and faster design closure.
Enhanced Hierarchical Flow allows all EDI applications to run up to 20x faster, while still enabling fairly accurate timing, area, and congestion analysis.
Low Power Design Complete Solution reduces test-pattern count and power consumption.
Fully automated Mixed Signal timing analysis provide significant reduction in iterations between analog and digital design teams, eliminates manual error-prone iterations, reduces TAT from weeks to hours.
16:15 – 17:00 Open discussion, round table
Для регистрации контактируете Владимира Лосева из МИЭТа: email@example.com
Какая из трех крупнейших компаний в области автоматизации электронного проектирования ваша любимая?
В каких еще московских вузах должны устраивать семинары Cadence, Synopsys и Mentor Graphics? (И MIPS/Imagination заодно?)