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Второй вариант первого зачета для вводного курса по Verilog и FPGA - Юрий Панчул [entries|archive|friends|userinfo]
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Второй вариант первого зачета для вводного курса по Verilog и FPGA [Mar. 26th, 2015|02:24 am]
Yuri Panchul
Второй вариант из первого зачета с простыми вопросами, который я составил для вводного курса по Verilog и FPGA, который я помогаю преподавать в одном из местных университетов Тимуру Палташеву из AMD. Как вы можете увидеть, это все те же вопросы из моего же зачета для курса по SoC, но без ассемблера и общих вопросов об индустрии.

Я вообще собираюсь скинуть в ЖЖ все 5 вариантов + 40 индивидуальных заданий. Критика приветствуется. Также просьба пройти зачет в голосовалке и сказать мне, сколько это заняло.








Midterm February 28, 2015  Name ____________________________________  Student ID __________________

1.2 Which waveform is the result of the simulation below?

module design (input a, input b, output o);

    assign o = ~ a | ~ b;

endmodule

module tb;

    logic a, b, o;

    design design_inst (a, b, o);

    initial
    begin
        $dumpvars;
        $monitor ("%t a %b b %b o %b", $time, a, b, o);

        #10;
        a = 0; b = 0; #10;
        a = 1; b = 0; #10;
        a = 0; b = 1; #10;
        a = 1; b = 1; #10;
    end

endmodule

a)



b)



c)



d)



e)



2.2 Which waveform is the simulation result of Verilog code below?

module dut
(
    input              clk,
    input        [7:0] d,
    output logic [7:0] q
);
    logic [7:0] r;

    always @(posedge clk)
    begin
        r <= d;
        q <= r;
    end

endmodule

module testbench;

    logic clk;
    logic [7:0] d, q;

    dut dut (clk, d, q);

    initial
    begin
       clk = 0;

       forever
           #10 clk = ! clk;
    end

    initial
    begin
        $dumpvars ();

        for (int i = 0; i < 10; i++)
        begin
            @(posedge clk);
            #15;
            d = i;
        end

        $finish;
    end

endmodule

a)



b)



c)



3.2 What schematics correspond to Verilog code below?

module dut
(
    input              clk,
    input        [7:0] d,
    output logic [7:0] q
);
    always @(posedge clk)
        q <= d;

endmodule



4.2 What Finite State Machine (FSM) state diagram correspond to Verilog code below?

module dut
(
    input  clk,
    input  resetn,
    input  a,
    output b
);
    logic [1:0] state;

    always @(posedge clk)
        if (! resetn)
            state <= 0;
        else
            case (state)
            0: state <= a ? 1 : 2;
            1: state <= 2;
            2: state <= 3;
            3: state <= 0;
            endcase

    assign b = (state == 2);

endmodule



5.2 What kind of delay is illustrated on the picture below (marked by "?")?

a) Clock-to-Q Propagation delay:
tpcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing)

b) Clock-to-Q Contamination delay:
tccq = time after clock edge that Q might be unstable (i.e., start changing)

c) Skew: difference between two clock edges. The clock doesnt arrive at all registers at same time



6.2 What kind of timing constraint is illustrated on the picture below (marked by "?")?

a) Setup time: tsetup = time before clock edge data must be stable (i.e. not changing)

b) Hold time: thold = time after clock edge data must be stable

c) Aperture time: ta = time around clock edge data must be stable (ta = tsetup +  thold)

d) Tc = minimum and maximum delays between registers



7.2 Which rule for signal assignment is violated in the following code?

a) Synchronous sequential logic: use always @(posedge clk) or always_ff @(posedge clk)
and nonblocking assignments (<=)    

        always_ff @ (posedge clk)
		   q <= d; // nonblocking

b) Simple combinational logic: use continuous assignments (assign)

             assign y = a & b; 

c) More complicated combinational logic: use always @* or always_comb and blocking assignments (=)

d) Assign a signal in only one always statement or continuous assignment statement

e) This code does not violate any rules for signal assignment

module dut
(
    input              clk,
    input        [7:0] d,
    output logic [7:0] q
);

    always @(posedge clk)
        if (d == 3)
            q <= 4;

    always @(posedge clk)
        if (d == 7)
            q <= 1;

endmodule

8.2 Suppose you are using the following module
to generate low-frequency clock using 8 MHz clock.
What will be the resulting frequencies
of clock_for_debouncing and clock_for_display?

a) 47.6 Hz and 763 Hz
b) 95.3 Hz and 1.53 KHz
c) 76.2 Hz and 1.22 KHz
d) 7.63 Hz and 122 Hz
e) 23.8 Hz and 381 Hz

module clock_divider
(
    input  clock,
    input  reset,
    output clock_for_debouncing,
    output clock_for_display
);

    reg [19:0] counter;

    always @(posedge clock)
    begin
        if (reset)
            counter <= 0;
        else
            counter <= counter + 1;
    end

    assign clock_for_debouncing = counter [19];
    assign clock_for_display    = counter [15];

endmodule

9.2 What is the function of the resistor in this particular circuit?

a) To protect LED from excessive current
b) Pullup - to provide the default value 1 for the input
c) Pulldown - to provide the default value 0 for the input
d) All the above
e) This resistor does not have any function in this circuit



Test written by Yuri Panchul
Sources of pictures:

Slides from Steve Harris and Sarah Harris that accompany textbook
Digital Design and Computer Architecture, Second Edition by David Harris and Sarah Harris, 2012
http://tinkerlog.com/2009/04/05/driving-an-led-with-or-without-a-resistor/
http://learn.sparkfun.com/tutorials/pull-up-resistors
http://ieeetamu.org/mcc/wsref/



Poll #2005445 Второй вариант первого зачета для вводного курса по Verilog и FPGA

1.2 Which waveform is the result of the simulation below?

a)
0(0.0%)
b)
1(25.0%)
c)
3(75.0%)
d)
0(0.0%)
e)
0(0.0%)

2.2 Which waveform is the simulation result of Verilog code below?

a)
0(0.0%)
b)
0(0.0%)
c)
4(100.0%)

3.2 What schematics correspond to Verilog code below?

a)
0(0.0%)
b)
4(100.0%)
c)
0(0.0%)

4.2 What Finite State Machine (FSM) state diagram correspond to Verilog code below?

a)
0(0.0%)
b)
0(0.0%)
c)
0(0.0%)
d)
0(0.0%)
e)
4(100.0%)

5.2 What kind of delay is illustrated on the picture below?

a) Propagation delay: tpd = max delay from input to output
3(75.0%)
b) Contamination delay: tcd = min delay from input to output
1(25.0%)
c) Skew: difference between two clock edges. The clock doesn’t arrive at all registers at same time.
0(0.0%)

6.2 What kind of timing constraint is illustrated on the picture below?

a) Setup time: tsetup = time before clock edge data must be stable (i.e. not changing)
0(0.0%)
b) Hold time: thold = time after clock edge data must be stable
0(0.0%)
c) Aperture time: ta = time around clock edge data must be stable (ta = tsetup + thold)
4(100.0%)
d) Tc = minimum and maximum delays between registers
0(0.0%)

7.2 Which rule for signal assignment is violated in the following code?

a) Synchronous sequential logic: use always @(posedge clk) or always_ff @(posedge clk) and nonblocking assignments
0(0.0%)
b) Simple combinational logic: use continuous assignments (assign...)
0(0.0%)
c) More complicated combinational logic: use always @* or always_comb and blocking assignments
0(0.0%)
d) Assign a signal in only one always statement or continuous assignment statement
3(75.0%)
e) This code does not violate any rules for signal assignment
1(25.0%)

8.2 What will be the resulting frequencies of clock_for_debouncing and clock_for_display?

a) 47.6 Hz and 763 Hz
0(0.0%)
b) 95.3 Hz and 1.53 KHz
0(0.0%)
c) 76.2 Hz and 1.22 KHz
0(0.0%)
d) 7.63 Hz and 122 Hz
4(100.0%)
e) 23.8 Hz and 381 Hz
0(0.0%)

9.2 What is the function of the resistor in this particular circuit?

a) To protect LED from excessive current
4(100.0%)
b) Pullup - to provide the default value 1 for the input
0(0.0%)
c) Pulldown - to provide the default value 0 for the input
0(0.0%)
d) All the above
0(0.0%)
e) This resistor does not have any function in this circuit
0(0.0%)


Было бы круто если бы кто-нибудь показал мне, как делать такие зачеты интерактивными, причем показал бы не ссылкой на сайт интерактивных экзаменов, а используя в качестве примера этот зачет. Я специально попросил не кидать мне ссылки, а показать на моем примере, потому что я уже опробовал несколько таких ссылок и во всех оказались проблемы либо с картинками в качестве ответов, либо с форматированием фрагментов кода.
LinkReply

Comments:
[User Picture]From: fabless
2015-03-26 09:36 am (UTC)
Написать медиа курс на C# и Flash
(Reply) (Thread)
[User Picture]From: panchul
2015-03-26 02:53 pm (UTC)
Надо бы найти энтузиаста, кто этим займется
(Reply) (Parent) (Thread)
[User Picture]From: fabless
2015-03-27 09:53 am (UTC)
Я могу модель клиент(flash)-сервер(C#) для таких тестов написать для публикации в Web, но только через несколько недель
(Reply) (Parent) (Thread)
[User Picture]From: Николай Пузанов
2015-03-26 10:41 am (UTC)
6 минут. Я сдал?
Что-то я поспешил, по всей видимости :)

Edited at 2015-03-26 01:48 pm (UTC)
(Reply) (Thread)
[User Picture]From: panchul
2015-03-26 02:53 pm (UTC)
Все правильно кроме первого, в котором вы наверное перепутали, к чему относится картинка - к верху или низу
(Reply) (Parent) (Thread)
[User Picture]From: muzl_ca
2015-03-26 10:59 am (UTC)
Вот было бы здорово пройти созданный по вашим материалам онлайн-курс как на stepic.org или hexlet.io
(Reply) (Thread)
[User Picture]From: dimaviolinist
2015-03-26 12:59 pm (UTC)
"...либо с форматированием фрагментов кода."
Сделать фрагменты кода в виде картинок.
(Reply) (Thread)
From: mashashama
2015-03-26 03:29 pm (UTC)
15 минут
(Reply) (Thread)
[User Picture]From: panchul
2015-03-26 03:32 pm (UTC)
Хорошо, все правильно
(Reply) (Parent) (Thread)
From: mashashama
2015-03-26 05:44 pm (UTC)
Формальность: во втором вопросе "... the simulation result of Verilog code below", но в коде используется тип logic, относящийся к SystemVerilog.
(Reply) (Thread)
[User Picture]From: urri_urri
2015-03-27 10:56 am (UTC)
10 мин. На 4 вопрос нет правильного ответа
(Reply) (Thread)
[User Picture]From: panchul
2015-03-27 09:03 pm (UTC)
*** На 4 вопрос нет правильного ответа ***

Претензии к альтеровской программе рисующей диаграммы. Она учитывает синхронный ресет


UPD: Один вопрос вы ответили неправильно

Edited at 2015-03-27 09:05 pm (UTC)
(Reply) (Parent) (Thread)
[User Picture]From: urri_urri
2015-03-31 11:28 am (UTC)
Да, в 7. Моя невнимательность.
(Reply) (Parent) (Thread)